The invention relates to technology for implementing electronic design automation tools, and in particular, to design tools that perform verification of rules for an integrated circuit (“IC”) design.
An IC is a small electronic device typically formed from semiconductor material. Each IC contains a large number of electronic components, e.g., transistors, that are wired together to create a self-contained circuit device. The components and wiring on the IC are materialized as a set of geometric shapes that are placed and routed on the chip material. During placement, the location and positioning of each geometric shape corresponding to an IC component are identified on the IC layers. During routing, a set of routes are identified to tie together the geometric shapes for the electronic components.
One or more verification processes are performed on the IC layout to ensure that the design abides by all of the detailed rules and parameters that have been specified for the manufacturing process, e.g., during design rule checking (“DRC”). The design rules are usually provided by a foundry as part of an organized rule deck. Violating even a single foundry rule runs the risk that the silicon product will be manufactured correctly or will not work for its intended purpose. Therefore, it is critical that thorough verification processing is performed before finalizing an IC design.
Rule verification may be performed frequently and at many stages of the IC design process. For example, verification may be used during design and at tape-out to ensure compliance with physical and electrical constraints imposed by the manufacturing process. In addition, verification may be performed during the design process, such as during the placement and routing process, to identify legal configurations of objects in a layout.
There are many types of design rules that are used to implement an IC design. A common type of design rule is the “spacing” rule. Spacing rules are established to ensure that adequate spacing exists between any two objects/shapes on the IC design. These rules are usually established by the foundry that will produce the IC chip.
“Width-dependent” spacing or clearance rules may also be established for an IC design. With modern, advanced technology, the minimum spacing between two objects on the IC design may be relative to the width of the two metal shapes. For example, if the metal width is X, then the spacing between this metal with the next space to the adjacent metal may need to be distance d. If the metal width is 2×, then the spacing between this metal with the next space to the adjacent metal may need to be wider, e.g., a distance of 1.5 d.
As modern IC designs become larger and more complex over time, greater numbers of circuit components are needed on the IC to implement those designs. This means that more and smaller shapes at greater complexities are placed on IC layout in closer proximities to each other. This problem is exacerbated by constantly improving IC manufacturing technologies that can create IC chips at ever-smaller feature sizes, which allows increasingly greater quantities of transistors to be placed within the same chip area, as well resulting in more complex physical and lithographic effects during manufacture. As a result, it becomes more and more difficult for design tools to adequately and efficiently perform verification of spacing and clearance rules.
Therefore, there is a need for improved techniques to address and verify spacing and clearance rules for modern IC designs.